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| SL74HCT374 Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS The SL74HCT374 is identical in pinout to the LS/ALS374. The SL74HCT374 may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. Data meeting the setup and hold time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip-flops, but when Output Enable is high, the outputs are forced to the high-impedance state; thus, data may be stored even when the outputs are not enabled. * TTL/NMOS-Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A ORDERING INFORMATION SL74HCT374N Plastic SL74HCT374D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 20=VCC PIN 10 = GND Output Enable L L L H L,H, X Inputs Clock D H L X X Output Q H L no change Z X = don't care Z = high impedance SLS System Logic Semiconductor SL74HCT374 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 35 75 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HCT374 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 0.1 0.5 85 C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 1.0 5.0 125 C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 1.0 10 A A V Unit VIH VIL VOH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 6.0 mA 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 V V V VOL Maximum Low-Level Output Voltage VIN= VIL or VIH IOUT 20 A VIN= VIL or VIH IOUT 6.0 mA IIN IOZ Maximum Input Leakage Current Maximum Three State Leakage Current VIN=VCC or GND Output in High-Impedance State VIN =VIH or VIL VOUT=VCC or GND VIN=VCC or GND IOUT=0A VIN=2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0A ICC Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current 5.5 4.0 40 160 A ICC -55C 25C to 125C 2.4 mA 5.5 2.9 SLS System Logic Semiconductor SL74HCT374 AC ELECTRICAL CHARACTERISTICS(VCC =5.0 V 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol fmax tPLH, t PHL tPLZ, t PHZ tPZH, t PZL tTLH, t THL CIN COUT Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay, Clock to Q (Figures 1 and 4) Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Flip-Flop) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 25 C to -55C 30 31 30 30 12 10 15 85C 24 39 38 38 15 10 15 125C 20 47 45 45 18 10 15 Unit MHz ns ns ns ns pF pF Typical @25C,VCC=5.0 V 65 pF TIMING REQUIREMENTS (VCC =5.0 V 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol tSU th tw tr, tf Parameter Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3) Minimum Pulse Width, Clock (Figure 1) Maximum Input Rise and Fall Times (Figure 1) 25 C to -55C 12 5.0 12 500 85C 15 5.0 15 500 125C 18 5.0 18 500 Unit ns ns ns ns SLS System Logic Semiconductor SL74HCT374 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit Figure 5. Test Circuit EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor |
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